The present invention relates to built-in self test circuitry (BIST), and, more particularly, to an all digital built-in self-test circuit for phase-locked loops.
Phase-locked Loops (PLLs) are used for a variety of applications in mixed-signal and digital systems. Some of the typical applications include (1) generating clocks of different frequencies from a reference clock, (2) generating a low jitter clock, (3) extracting a data-synchronous clock from serially communicated data, and (4) generating a stable clock from a noisy clock signal. Tightly controlled performance parameters are a must for satisfactory operation of mixed-signal or digital circuitry in which the PLL is embedded. Specifically, when PLLs are used as building blocks to provide clock signals in mixed-signal circuitry, the clock signals generated by the PLL must be stable.
Ideally, as shown in FIG. 1, pulse width, P, period, T, and frequency of a clock signal should remain the same from cycle to cycle. Due to noise generated in and in close proximity to the PLL circuit, however, the period can vary around a mean value. Fluctuation of the period of a clock signal relative to an ideal base is known as jitter. Since noise is the cause of this fluctuation, one may assume that jitter is a random statistical phenomena, Gaussian in nature. FIG. 2 illustrates a jittery clock compared with an ideal jitter-free clock.
Assuming that n period measurements are done on a clock, measured periods can be represented by [T1, T2, . . . Tn]. The mean period of the clock (T) is given by the equation:                     T        =                                            ∑                              i                =                1                            n                        ⁢                          T              i                                n                                    (        1        )            
The standard deviation of the period is known as root mean square (RMS) jitter RMS jitter is given by the equation:                               J          rms                =                                                            ∑                                  i                  =                  1                                n                            ⁢                                                (                                                            T                      i                                        -                    T                                    )                                2                                      n                                              (        2        )            
Peak-to-peak jitter is given by the equation:
Jpktopk=max[T1, . . . , Tn]xe2x88x92min[T1, . . . , Tn]xe2x80x83xe2x80x83(3)
Jitter and duty ratio are two important parameters of the PLL output clock; where duty ratio of the clock signal is defined as the ratio of pulse width to the period:                     P        T                            (        4        )            
Many commercial automatic test equipment (ATE) like Teradyne""s(trademark) A580, Catalyst etc. incorporate a time jitter digitizer (TJD) circuit to measure these parameters during production testing. The TJD circuit can capture the times at which a particular event such as rising or falling of a clock edge takes place very accurately. These events are stored in an array which can be post-processed using equations 1-4 to calculate various clock parameters. Various methods of measuring the clock parameters using the TJD circuit are described in detail in xe2x80x9cTest Technique Note MS30: Analog Jitter Demodulation,xe2x80x9d Teradyne Inc. (1991), which is incorporated by reference herein.
Although TJD circuits are fairly accurate in the sub-nanosecond range, they are expensive. Hence, it is not feasible to implement these TJD circuits in low-cost production testers, such as Texas Instrument""s(trademark) V-series low-cost production testers. Accordingly, the TJD circuit is not commonly found in low-cost production testers.
Another approach uses the incorporation of built-in-self-test (BIST) circuitry. A BIST circuit implements the functions of an ATE on-chip by applying the test signal to the circuit under test (CUT) and analyzing its response to verify if the circuit is functioning properly. Due to the advancements in the process technology, the cost of implementing more functions on an integrated circuit is decreasing. The use of BIST circuitry leverages off of this advantage by reducing the production test time and allowing the use of low-cost testers in production testing. Thereby, BIST circuitry reduces the production test cost of integrated circuits.
Another approach, disclosed in U.S. Pat. No. 5,663,991 which is incorporated by reference herein, describes a BIST scheme to measure the peak-to-peak jitter of PLL circuit. A low-jitter clock is used as a reference to characterize the jitter of the PLL. A delay chain is realized using a string of inverters to delay the reference clock and find the position of the jittery PLL clock edge. As is required, a calibration system including analog parts controls the delays of the inverters. Since parametric specifications of the analog parts can. deviate from the expected values due to process variations, to guarantee accurate measurement of the PLL jitter, the calibration circuitry must be tested to determine whether it meets its specifications. Unfortunately, this patent does not include circuitry or a method of testing the calibration circuitry. Thus, accuracy or the lack thereof tends to be an issue with the present approach. Moreover this approach requires a low-jitter clock that is used as a reference clock for characterizing the jitter of the PLL.
Sunter et al. presents another BIST scheme for measuring PLL specifications in the publication entitled xe2x80x9cBIST for Phase-Locked Loops in Digtal Applications,xe2x80x9d International Test Conference, IEEE Computer Society Press, p. 532-540 (1999). They also incorporate the use of a low-jitter clock as a reference to measure PLL jitter. The BIST scheme uses a string of inverters, 10-24, to delay the reference clock as shown in FIG. 3. A portion of the delay chain is identified using digital logic such that the total delay of this portion is equal to peak-to-peak or the RMS jitter of the PLL. Two ring oscillators are then formed by connecting (1) all the inverters, 10-16, from the beginning of the delay chain to the beginning of the identified portion of the delay chain (T1) or (2) all the inverters, 10-24, from the beginning of the delay chain to the end of the identified portion of the delay chain (T2). This BIST scheme provides the measurement of the period of these ring oscillators where the peak-to-peak and RMS jitter is given by the difference between these periods. The delays of the inverters, however, during jitter measurement can be different from that when connected as ring oscillator due to interaction between the delay chain and the PLL. Thus, this arrangement has a tendency to lead to inaccurate jitter measurements.
Furthermore, the BIST schemes described above assume the availability of a low-jitter reference clock. Yet, low-cost testers often do not include low-jitter clocks. Moreover, when low-jitter reference clocks are used, the clock signal must be routed carefully to the PLL since jitter can be injected into the clock signal in route to the PLL. Additionally, using on-chip oscillators for generating the clock signal is not recommended since its frequency and jitter can affect the BIST results. Furthermore, other proposed solutions are cost prohibitive and require significant vendor intrusion into one""s design environment.
Thus, there is a need for a cost efficient, all digital BIST scheme for measuring PLL jitter in the sub-nano seconds that does not include external reference clocks nor on-chip oscillators.
To address the above-discussed deficiencies of the BIST circuits that measure jitter, the present invention teaches an integrated circuit chip having a built-in circuit for measuring error of a phase lock loop output clock signal. The circuit includes a short-pulse generator that generates a short-pulse signal having the same pulse width as the phase lock loop output clock signal. Accordingly, a delay chain, including a plurality of delay elements, generates N delayed pulses from the short-pulse signal. A hit-pulse generator receives the N delayed pulses and compares each delayed pulse with the phase lock loop output clock signal 2K times, such that the hit-pulse generator also generates a hit-pulse when both signals are high. It also generates a hit count which represents the number of hit-pulses. After each of the N delayed pulses are compared with the clock signal 2k times, a comparator compares a predetermined set of threshold values corresponding to the cumulative distribution of jitter for a PLL clock signal with the hit count. When the hit count and one of the predetermined set of threshold values are equivalent, the storage unit stores the value of N. A processing unit calculates the error of the PLL clock signal using each stored value of N which directly relates to the cumulative distribution of jitter found in the PLL clock signal.
Advantages of the present invention include but are not limited to an efficient, modular, testable BIST circuit which utilizes less time to test. Furthermore, since the BIST solution in accordance with the present invention is all-digital, it can be tested using standard digital test techniques. For a further savings, this BIST circuit is capable of running in tandem with other tests. Thus, a considerable amount of production test time can be saved for mixed-signal integrated circuits which use expensive mixed-signal ATEs.
The most significant advantage of the present invention is that the external reference clock is not required. Thus, a BIST circuit in accordance with the present invention provides PLL testing in low-cost testers which aligns with the present and future technological needs of semiconductor testing. Particularly, since semiconductor manufacturers are advancing towards low cost testing and low cost testers where external reference clocks having low jitter may not be readily available.